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ES9018-2M DS Rev 0.9

CONFIDENTIAL ADVANCE INFORMATION

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The ES9018K2M SABRE32 Reference DAC is a high-performance 32-bit, 2-channel audio D/A converter targeted for audiophile-grade portable applications such as mobile phones and digital music players, consumer applications such as Blu-ray players, audio pre-amplifiers and A/V receivers, as well as professional applications such as recording systems, mixer consoles and digital audio workstations. Using the critically acclaimed ESS patented 32-bit Hyperstream? DAC architecture and Time Domain Jitter Eliminator, the ES9018K2M SABRE32 Reference DAC delivers a DNR of up to 127dB and THD+N of 120dB, a performance level that will satisfy the most demanding audio enthusiasts. The ES9018K2M SABRE32 Reference DAC’s 32-bit Hyperstream? architecture can handle up to 32-bit 384kHz PCM data via I2S, DSD-11.2MHz data as well as mono mode for highest performance applications. Both synchronous and ASRC (asynchronous sample rate conversion) modes are supported. The ES9018K2M SABRE32 Reference DAC comes in 28-QFN package and consumes less than 40mW in normal operation mode (<1mW in standby mode).

FEATURE
Patented 32-bit Hyperstream? DAC o 127dB DNR o -120dB THD+N Patented Time Domain Jitter Eliminator 64-bit accumulator and 32-bit processing Integrated DSP Functions

DESCRIPTION
o o o o o o o o o o o o Industry’s highest performance 32-bit mobile audio DAC with unprecedented dynamic range and ultra low distortion Supports both synchronous and ASRC (asynchronous sample rate converter) modes Unmatched audio clarity free from input clock jitter Distortion free signal processing Click-free soft mute and volume control Programmable Zero detect De-emphasis for 32, 44.1 and 48kHz sampling Mono or stereo output in current or voltage mode based on performance criterion Allows software control of DAC features Minimizes PCB footprint Maximizes battery life Supports SPDIF, PCM (I2S, LJ 16-32-bit) or DSD input

Customizable output configuration I2C control 28-QFN (5mm x 5mm) package <40mW operational power <1mW standby power Versatile digital input

APPLICATIONS
? ? ? ? Mobile phones / Tablets / Digital music players / Portable multimedia players Blu-ray / SACD / DVD-Audio player Audio preamplifier and A/V receiver, Professional audio recording systems / Mixing consoles / Digital audio workstation

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CONFIDENTIAL ADVANCE INFORMATION Rev. 0.9

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ES9018K2M Datasheet

FUNCTIONAL BLOCK DIAGRAM
RESETB GPIO1 GPIO2 SDA SCL

CONTROL INTERFACE

ES9018K2M
ASRC & Jitter Reduction
DPLL

OVERSAMPLING FILTER DATA[2:1] DATA_CLK PCM / DSD / SPDIF Interface
Fast/Slow roll-off (PCM) 50/60/70kHz (DSD) De-emphasis (PCM) Volume Control Soft Mute Zero Detect

32-bit HyperstreamTM DAC (2x)

Dynamic Matching (2x)

DACL, DACR DACLB, DACRB

XI / MCLK XO

OSC

Core Voltage

Core & IO Power Supply

DAC Power Supply

VCCA (3.3V)

DVDD

DVCC (1.8/3.3V)

GND

AVCC_L, AVCC_R (3.3V)

TYPICAL MOBILE APPLICATION DIAGRAM

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Headphones

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Speakers Earpiece

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CONFIDENTIAL ADVANCE INFORMATION Rev. 0.9

ES9018K2M Datasheet

PIN LAYOUT

DGND N.C. SCL SDA ADDR XO XI (MCLK)

1 2 3 4 5 6 7

28 27 26 25 24 23 22 21 20 19 18 17 16 15

RESETB DATA_CLK DATA1 DATA2 GPIO1 GPIO2 N.C.

(6.0 4)1

DVDD DGND N.C. DVCC VCCA AVCC_R AVCC_L

3

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AGND DACR DACRB AGND_R AGND_L DACL DACLB

8 9 10 11 12 13 14

CONFIDENTIAL ADVANCE INFORMATION Rev. 0.9

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ES9018K2M Datasheet

PIN DESCRIPTION
Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Name
DGND N.C. SCL SDA ADDR XO XI (MCLK) AGND DACR DACRB AGND_R AGND_L DACL DACLB AVCC_L AVCC_R VCCA DVCC N.C. DGND DVDD

Pin Type
GROUND I I/O I AO AI GROUND AO AO GROUND GROUND AO

Reset State

Pin Description
Ground

Tri-stated Tri-stated Tri-stated Floating Floating Driven to ground Driven to ground

I2C SCL I2C SDA I2C Address Select XTAL Out XTAL / MCLK In Analog Ground Differential Positive Analog Output Right Differential Negative Analog Output Right Analog Ground Analog Ground Differential Positive Analog Output Left Differential Negative Analog Output Left Analog AVCC for Left Channel Analog AVCC for Right Channel Analog 1.8 or 3.3V for OSC Digital 1.8 or 3.3V Ground Digital Core Voltage This could be internally generated with a regulator from DVCC, or externally supplied. Please refer to the section DVDD Supply on p.7.

AO
POWER POWER POWER POWER GROUND POWER (Internal / External) I/O I/O I I/O I/O I

Driven to ground Driven to ground

22 23 24 25 26 27 28

N.C. GPIO2 GPIO1 DATA2 DATA1 DATA_CLK RESETB

Tri-stated Tri-stated Tri-stated Tri-stated Tri-stated Tri-stated

GPIO 2 GPIO 1 DSD Data2 OR PCM Data CH1/CH2 or SPDIF Input 2 Master mode off: Input for DSD Data1 OR PCM Frame Clock or SPDIF Input 3 Master mode on: Output for PCM Frame Clock Master mode off: Input for PCM Bit Clock OR DSD Bit Clock OR SPDIF Input 1 Master mode on: Output for PCM Bit Clock Master Reset / Power Down (active low)

Note: There are 3 N.C. (No Connect) pins.

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FUNCTIONAL DESCRIPTION
NOTATATIONS for Sampling Rates Mode DSD Serial (PCM) Normal Mode SPDIF fs DATA_CLK/64 DATA_CLK/64 SPDIF Sampling Rate Fs DSD data rate DATA_CLK/64 SPDIF Sampling Rate

PCM, SPDIF and DSD Pin Connections
The following tables show how the pins are used for PCM and DSD audio formats. PCM Audio Format Note: XI clock (MCLK) must be > 192*Fs when using PCM input (normal mode). Pin Name DATA1 DATA2 DATA_CLK Description Frame clock 2-channel PCM serial data Bit clock for PCM audio format

Master Mode (32-bit data only) When Register #1 ‘input_select’ is set to 2’d0 (I2S) and ‘i2s_length’ is set to 2’d2 (32-bit), the DAC can become a master for Bit Clock and Frame Clock by setting Register #9 ‘master clock enable’ to 1’b1. The Bit Clock frequency can be configured to MCLK/4, MCLK/8 or MCLK/16 by setting Register #9 ‘clock divider select’ to 2’b00, 2’b01 or 2’b10. GPIO 1 (or 2) can be configured to output MCLK by setting Register #8 gpio1_cfg (or gpio2_cfg) to 4’d3.
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SPDIF Audio Formant Note: XI clock (MCLK) must be > 386*Fs when using SPDIF input. Up to 3 SPDIF inputs can be connected to the 3-to-1 mux, selectable via register “spdif_sel”. Pin Name DATA1 DATA2 DATA_CLK Description SPDIF input 3 SPDIF input 2 SPDIF input 1

DSD Audio Format Note: XI clock (MCLK) must be > 3*Fs when using DSD input. Pin Name DATA[1:2] DATA_CLK Description 2-channel DSD data input Bit clock for DSD data input

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ES9018K2M Datasheet

FEATURE DESCRIPTION
Soft Mute
When Mute is asserted the output signal will ramp to the -∞ level. When Mute is reset the attenuation level will ramp back up to the previous level set by the volume control register. Asserting Mute will not change the value of the volume control register. The ramp rate is 0.0078125*FS/(2^(vol_rate-5)) dB/s, where FS = DATA_CLK/64 in PCM serial or DSD modes, or SPDIF sampling rate in SPDIF mode.

Automute
During an automute condition the ramping of the volume of each DAC to -∞ can now be programmatically enabled or disabled. o In PCM serial mode, “AUTOMUTE” will become active once the audio data is continuously below the threshold set by <Register Automute_lev>, for a length of time defined by 2096896/(<Register#9>*DATA_CLK) Seconds. o In SPDIF mode, “AUTOMUTE” will become active once the audio data is continuously below the threshold set by <Register Automute_lev>, for a length of time defined by 2096896/(<Register#9>*(64*Fs) Seconds, where Fs is the SPDIF sampling rate. o In the DSD Mode, “AUTOMUTE” will become active when any 8 consecutive values in the DSD stream have as many 1’s and 0’s for a length of time defined by 2096896/(<Register Automute_time>*DATA_CLK) Seconds. The following table summarizes the conditions. Mode PCM SPDIF DSD Detection Condition Data is continuously lower than <Register Automute_lev > Data is continuously lower than <Register Automute_lev > Equal number of 1s and 0s in every 8 bits of data Time 2096896/(<Register Automute_time >*DATA_CLK) 2096896/(<Register Automute_time >*(64*Fs)) where Fs is the SPDIF sampling rate 2096896/(<Register Automute_time >*DATA_CLK)

Volume Control
Each output channel has its own attenuation circuit. The attenuation for each channel is controlled independently. Each channel can be attenuated from 0dB to –127dB in 0.5dB steps. Each 0.5dB step transition takes up to 128 intermediate levels, depending on the vol_rate register setting. The result being that the level changes are done using small enough steps so that no switching noise occurs during the transition of the volume control. When a new volume level is set, the attenuation circuit will ramp softly to the new level.

Master Trim
The master trim sets the 0dB reference level for the volume control of each DAC. The master trim is programmable via registers 20-23 and is a 32bit signed number. Therefore it should never exceed 32'h7FFFFFFF (as this is full-scale signed).

All Mono Mode
An all mono mode where all DACs are driven from the same source is supported. This can be useful for high-end audio applications. The source data for all DACs can be programmatically configured to be either CH1 or CH2.

De-emphasis
The de-emphasis feature is included for audio data that has utilized the 50/15uS pre-emphasis for noise reduction. There are 3 de-emphasis filters, one for 32 kHz, 44.1 kHz and 48 kHz.

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ES9018K2M Datasheet

SPDIF Data Select
An SPDIF source multiplexer allows for up to three SPDIF sources to be connected to the data pins. An internal programmable register (spdif_sel) is used to select the appropriate data pin to decode.

System Clock (XI / MCLK)
A system clock is required for proper operation of the digital filters and modulation circuitry. Maximum clock frequency is 100MHz. The system clock must also satisfy: Data Type DSD Data Serial Normal Mode SPDIF Data Valid MCLK Frequencies 100MHz > MCLK > 3*Fs , Fs = 2.8224MHz (x 1, 2 or 4) 100MHz > MCLK > 192*Fs, Fs ≤ 384kHz 100MHz > MCLK > 386*Fs, Fs ≤ 200kHz

Data Clock
DATA_CLOCK must be (2*i2s_length)*Fs for SERIAL, and Fs for DSD modes. For SPDIF mode, this pin is used for SPDIF input. This pin should be pulled low if not used.

Built-in Digital Filters
There are numerous applications for a stereo DAC so for added flexibility; two digital filter settings are possible, sharp roll-off and a slow roll-off for PCM mode.

DVDD Supply
Depending on the operating conditions, an external DVDD supply may be required, as shown in the following table: DVCC 1.8V XI / MCLK ≤ [TBD] 27MHz > [TBD] 27MHz 3.3V External DVDD Optional Required Optional Required Internal DVDD An internal +1.2V regulator will generate the required DVDD supply from DVCC. An internal +1.2V regulator will generate the required DVDD supply from DVCC.

≤ [TBD] 50MHz
> [TBD] 50MHz

Standby Mode
For lowest power consumption the followings should be performed to enter stand-by mode: ? Set the soft_start bit in register 14 to 1'b0 to ramp the DAC outputs (DACL, DACLB, DACR, DACRB) to ground. ? RESETB pin should be brought to low digital level to: o Shut off the DACs, Oscillator and internal regulator. o Force digital I/O pins (DATA_CLK, DATA1, GPIO1, GPIO2, SDA ) into tri-state mode o Reset all registers to default states ? If XI/MCLK is supplied externally, it should be stopped at logic low level To resume from standby mode, bring RESETB to high digital level and reinitialize all registers.

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ES9018K2M Datasheet Audio Interface Formats
Several interface formats are provided so that direct connection to common audio processors is possible. The available formats and their accompanying diagrams are listed in the following table. The audio interface format can be set by programming the registers.

LRCLK BCLK SIN 32-bit SIN 24-bit SIN 16-bit
 06%  

LEFT

RIGHT























/6% 06%

/6% 06%

 06%



























/6% 06%

/6% 06%

 06%



























/6% 06%

/6% 06%

LEFT JUSTIFIED FORMAT

LRCLK BCLK SIN 32-bit SIN 24-bit SIN 16-bit
 06%  

LEFT

RIGHT























/6% 06%

/6% 06%

 06%



























/6% 06%

/6% 06%

 06%



























/6% 06%

/6% 06%

I2S FORMAT

Note: for Left-Justified and I2S formats, the following number of BCLKs is present per (left plus right) frame: ? 16-bit mode: 32 BCLKs ? 24-bit mode: 48 BCLKs ? 32-bit mode: 64 BCLKs

DCLK DSD1, DSD2
D.. D0 D1 D2 D3 D4

DSD NORMAL MODE

DCLK DSD1, DSD2
D.. D.. D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 DSD PHASE MODE

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ES9018K2M Datasheet SERIAL CONTROL INTERFACE
The registers inside the chip are programmed via an I2C interface. The diagram below shows the timing for this interface. The chip address can be set to 2 different settings via the “ADDR” pin. The table below summarizes this.

ADDR 0 1

CHIP ADDRESS 0x90 0x92

Notes: 1. The “ADDR” pin is used to create the CHIP ADDRESS. (0x90, 0x92) 2. The first byte after the chip address is the “ADDRESS” this is the register address. 3. The second byte after the CHIP ADDRESS is the “DATA” this is the data to be programmed into the register at the previous “ADDRESS”.

6WDUW

6WDUW

6WRS

6WDUW

Parameter

Symbol Standard-Mode Fast-Mode Unit MIN MAX 100 1000 300 400 0.6 1.3 MIN MAX 0 0.6 1.3 0.6 0.6 0.3 100 400 300 300 400 kHz us us us us us s ns ns us us pF

SCL Clock Frequency START condition hold time LOW period of SCL HIGH period of SCL

fSCL tHD,STA tLOW tHIGH

0 4.0 4.7 4.0 4.7 0.3 250 4 4.7 -

START condition setup time (repeat) tSU,STA SDA hold time from SCL falling SDA setup time from SCL rising Rise time of SDA and SCL Fall time of SDA and SCL STOP condition setup time tHD,DAT tSU,DAT tr tf tSU,STO

Bus free time between transmissions tBUF Capacitive load for each bus line Cb

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ES9018K2M Datasheet

REGISTER SETTINGS
Register #0: System Settings
8 bit, Read-Write Register, Default=0x00 Bits [7] [6] [5] [4] [3] [2] [1] Mnemonic osc_drv reserved Default 0 0 0 0 0 0 0 Bit [7:4] Mnemonic osc_drv [0] soft_reset 0

Description Oscillator drive specifies the bias current to the oscillator pad. ? 4'b1111: shut down the oscillator ? 4'b1110: 1/4 bias ? 4'b1100: 1/2 bias ? 4'b1000: 3/4 bias ? 4'b0000: full bias (default) ? Other settings: reserved It is recommended to use the default setting. 1'b1 resets chip 1'b0 is normal operation (default)

[3:1] [0]

reserved soft_reset

Register #1: Input Configuration
8 bit, Read-Write Register, Default=0x8C Bits [7] [6] [5] [4] [3] [2] Mnemonic I2s_length i2s_mode auto_input_select Default 1 0 0 0 1 1 Bit [7:6] Mnemonic I2s_length [1] [0] input_select 0 0

[5:4]

i2s_mode

[3:2]

auto_input_select

[1:0]

input_select

Description 2'd0 = 16bit 2'd1 = 24bit 2'd2 or 2'd3 = 32bit (default) 2’d3 = LJ mode 2’d2 = I2S 2’d1 = LJ mode 2’d0 = I2S (default) 2'd0 = 'input select', 2'd1 = I2S or DSD, 2'd2 = I2S or SPDIF, 2'd3 = I2S, SPDIF or DSD (default) 2'd3 = DSD, 2'd2 = reserved, 2'd1 = SPDIF, 2'd0 = I2S (default)

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Register #4: Soft Volume Control 1 (Automute Time)
8 bit, Read-Write Register, Default=0x00 Bits [7] [6] [5] [4] [3] [2] [1] automute_time Mnemonic Default 0 0 0 0 0 0 0 Bit [7:0] Mnemonic automute_time [0] 0

Description Default of 8'd0 (Automute Disabled) Time in Seconds = 2096896/(automute_time*DATA_CLK) with DATA_CLK in Hz

Register #5: Soft Volume Control 2 (Automute Level)
8 bit, Read-Write Register, Default=0x68 Bits [7] [6] [5] [4] [3] [2] [1] automute_level Mnemonic automute_loopback Default 0 1 1 0 1 0 0 Bit [7] [6:0] Mnemonic automute_loopback automute_level [0] 0

Description 1'b0 disables automute_loopback (default) 1'b1 ramps to -infinity on automute The level (in 1dB increments) of the automute, default of 7'd104

Register #6: Soft Volume Control 3 and Deemphasis
8 bit, Read-Write Register, Default=0x42 Bits [7] [6] Mnemonic spdif_auto_deemph deemph_bypass Default 0 1 Bit [7] [6] [5:4] Mnemonic spdif_auto_deemph deemph_bypass deemph_sel [5] [4] deemph_sel 0 0 [3] reserved 0 [2] [1] [0] vol_rate 0 1 0

Description 1'b1 enables automatic deemphasis select in SPDIF mode 1'b0 disables automatic deemphasis select in SPDIF mode (default) 1'b1 disabled deemphasis filters (default) 1'b0 enables deemphasis filters 2’b00 = 32kHz (default) 2’b01 = 44.1kHz 2’b10 = 48kHz 2’b11 = RESERVED 3'd2 by default Sets the volume ramp rate to 0.0078125*FS/(2^(vol_rate-5)) dB/s

[3] [2:0]

reserved vol_rate

11

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Register #7: General Settings
8 bit, Read-Write Register, Default=0x80 Bits [7] [6] [5] [4] Mnemonic reserved filter_shape reserved Default 1 0 0 0 Bit [7:6] [5] [4] [3:2] Mnemonic reserved filter_shape reserved iir_bw Description 1'b1 = slow rolloff 1'b0 = fast rolloff (default) 2'd0 = 1.0757fs or 47.44kHz (fs=44.1kHz) - Normal mode (default) 2'd1 = 1.1338fs or 50k (fs=44.1kHz) 2'd2 = 1.3605fs or 60k (fs=44.1kHz) 2'd3 = 1.5873fs or 70k (fs=44.1kHz) This is a soft mute, which uses the ramping volume control. mute[0] ? 1’b1: Channel 1 (default of left channel) muted ? 1’b0: Channel 1 (default of left channel) unmuted (default) mute[1] ? 1’b1: Channel 2 (default of right channel) muted ? 1’b0: Channel 2 (default of right channel) unmuted (default) [3] [2] iir_bw 0 0 [1] [0] mute 0 0

[1:0]

mute

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Register #8: GPIO Configuration
8 bit, Read-Write Register, Default=0x10 Bits [7] [6] [5] [4] [3] [2] [1] [0] Mnemonic gpio2_cfg gpio1_cfg Default 0 0 0 1 0 0 0 0 Bit [7:4] Mnemonic gpio2_cfg Description Set GPIO 2 configuration. Default to 4’d1 (DPLL Lock Status). See GPIO Configuration Table below for meaning of all settings. Set GPIO 1 configuration Default to 4’d0 (Automute Status). See GPIO Configuration Table below for meaning of all settings.

[3:0]

gpio1_cfg

GPIO Configuration Table Setting 4'd0 4'd1 4'd2 4'd3 4'd4 Direction Output Output Output Output Output GPIO Function Automute status (active high) – asserted when Automute condition is met DPLL Lock status (active high) – asserted when DPLL is in lock Minimum Volume (active high) - asserted when volume of both the left and right channels has ramped to its minimum value (-127.5dB). MCLK DPLL Lock interrupt (active high) - asserted when DPLL Lock status changes state - reading register 64 clears the interrupt Automute Interrupt (active high) - asserted when Automute status changes state - reading register 64 clears the interrupt DPLL Lock or Automute interrupt (active high) - asserted when DPLL Lock or Automute status changes state - reading register 64 clears the interrupt Output low Used as input pin Pin status can be read from register 65. Sets DAC input (I2S/DSD/SPDIF) mode Mode definition is configured via register 21 Reserved Output high

4'd5

Output

4'd6

Output

4'd7 4'd8 4'd9 4'd10-14 4'd15

Output Input Input

Output

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Register #9: Master Mode Control
8 bit, Read-Write Register, Default=0x0 Bits [7] [6] [5] Mnemonic master clock enable clock divider select Default 0 0 0 Bit [7] [6:5] Mnemonic master clock enable clock divider select [4] reserved_0 0 [3] 0 [2] [1] [0] reserved 0 0 0

Description 1'b1 enables master mode (driving Bit clock and Frame Clock) 1'b0 disables master mode (default) 2'b00: Bit Clock frequency = MCLK/4 (default) 2'b01: Bit Clock frequency = MCLK/8 2b10: Bit Clock frequency = MCLK/16 2'b11: Bit Clock frequency = MCLK/16 Frame Clock frequency = Bit Clock frequency / 64 1'b0 (must be set to 1'b0)

[4] [3:0]

reserved_0 reserved

For correct operation, master mode should only be enabled when the DAC’s input mode is set to I2S, and when i2s_length is set to 32-bit and i2s_mode is set to I2S in register 1. When master mode is enabled, the DATA_CLK pin will output Bit Clock and the DATA1 pin will output Frame Clock at frequencies specified by clock divider select.

Register #11: Channel Mapping
8 bit, Read-Write Register, Default=0x02 Bits [7] [6] [5] [4] [3] Mnemonic spdif_sel ch2_analog_swap Default 0 0 0 0 0 Bit [7] [6:4] Mnemonic Reserved spdif_sel Description select the spdif data source 3’d0 = DATA_CLK (default) 3’d1 = DATA2 3’d2 = DATA1 3’d3 = GPIO1 3’d4 = GPIO2 3’d5-7: reserved 1'b0 = normal operation (default) 1'b1 = swap dac and dacb 1'b0 = normal operation (default) 1'b1 = swap dac and dacb 1'b0 = left 1'b1 = right (default) 1'b0 = left (default) 1'b1 = right [2] ch1_analog_swap 0 [1] ch2_sel 1 [0] ch1_sel 0

[3] [2] [1] [0]

ch2_analog_swap ch1_analog_swap ch2_sel ch1_sel

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ES9018K2M Datasheet

Register #12: DPLL/ASRC Settings
8 bit, Read-Write Register, Default=0x5A Bits [7] [6] [5] [4] [3] [2] [1] [0] Mnemonic dpll_bw_i2s dpll_bw_dsd Default 0 1 0 1 1 0 1 0 Bit [7:4] Mnemonic dpll_bw_i2s Description DPLL bandwidth setting for I2S and SPDIF modes 4’b0000 : 128x=0, No Bandwidth 4’b0001 : 128x=0, Lowest Bandwidth 4’b0010 : 128x=0, Low Bandwidth 4’b0011 : 128x=0, Med-Low Bandwidth 4’b0100 : 128x=0, Medium Bandwidth 4’b0101 : 128x=0, Med-High Bandwidth (default) 4’b0110 : 128x=0, High Bandwidth 4’b0111 : 128x=0, Highest Bandwidth 4’b1000 : 128x=1, No Bandwidth 4’b1001 : 128x=1, Lowest Bandwidth 4’b1010 : 128x=1, Low Bandwidth 4’b1011 : 128x=1, Med-Low Bandwidth 4’b1100 : 128x=1, Medium Bandwidth 4’b1101 : 128x=1, Med-High Bandwidth 4’b1110 : 128x=1, High Bandwidth 4’b1111 : 128x=1, Highest Bandwidth DPLL bandwidth setting for DSD mode 4’b0000 : 128x=0, No Bandwidth 4’b0001 : 128x=0, Lowest Bandwidth 4’b0010 : 128x=0, Low Bandwidth 4’b0011 : 128x=0, Med-Low Bandwidth 4’b0100 : 128x=0, Medium Bandwidth 4’b0101 : 128x=0, Med-High Bandwidth 4’b0110 : 128x=0, High Bandwidth 4’b0111 : 128x=0, Highest Bandwidth 4’b1000 : 128x=1, No Bandwidth 4’b1001 : 128x=1, Lowest Bandwidth 4’b1010 : 128x=1, Low Bandwidth (default) 4’b1011 : 128x=1, Med-Low Bandwidth 4’b1100 : 128x=1, Medium Bandwidth 4’b1101 : 128x=1, Med-High Bandwidth 4’b1110 : 128x=1, High Bandwidth 4’b1111 : 128x=1, Highest Bandwidth

[3:0]

dpll_bw_dsd

Register #13: Reserved
8 bit, Read-Write Register, Default=0x40

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Register #14: Soft Start Settings
8 bit, Read-Write Register, Default=0x8A Bits [7] [6] Mnemonic soft_start soft_start_on_lock Default 1 0 Bit [7] [6] [5] [4:0] Mnemonic soft_start soft_start_on_lock mute_on_lock soft_start_time [5] mute_on_lock 0 [4] [3] [2] [1] [0] soft_start_time 0 1 0 1 0

Description 1'b0: Ramp the output stream to ground in anticipation of going into standby mode 1'b1: Normal operation (default) - ramp the output stream to ?* AVCC_L/R 1’b1: Force output low when lock is lost 1'b0: Do not force output low when lock is lost (default) 1’b1: Force a mute when lock is lost 1’b0: Do not force a mute when lock is lost (default) Time for soft start ramp = 4096*2^(soft_start_time+1)/MCLK seconds (where MCLK is measured in Hz). The valid range of soft_start_time is from 0 to 20.

Register #15: Volume 1
8 bit, Read-Write Register, Default=0x00 Bits [7] [6] [5] [4] [3] [2] [1] Mnemonic volume1 Default 0 0 0 0 0 0 0 Bit [7:0] Mnemonic Volume1 [0] 0

Description Default to 8'd0 - 0dB to -127.5dB 0.5dB steps

Register #16: Volume 2
8 bit, Read-Write Register, Default=0x00 Bits [7] [6] [5] [4] [3] [2] [1] Mnemonic volume2 Default 0 0 0 0 0 0 0 Bit [7:0] Mnemonic volume2 [0] 0

Description Default to 8'd0 - 0dB to -127.5dB 0.5dB steps

Register #20-17: Master Trim
32 bit, Read-Write Register, Default=32’h7ffffff. Reg 20 are the MSB’s, Reg 17 are the LSB’s. Bits [31:0] Mnemonic master_trim Default 32'h7fffffff This is a 32 bit value that sets the 0dB level for all volume controls. This is a signed number, so it should never exceed 31 32'h7fffffff (which is 2 - 1).

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Register #21: Input Select Control
8 bit, Read-Write Register, Default=0x00 Bits [7] [6] [5] [4] Mnemonic gpio_input_sel2 gpio_input_sel1 Default 0 0 0 0 Bit [7:6] Mnemonic gpio_input_sel2 [3] 0 [2] [1] [0] reserved 0 0 0

[5:4]

gpio_input_sel1

Description Selects the input to be used when the GPIO pin configured as input select (i.e. Register#8 gpio1_cfg = 4’d9 or Register#8 gpio2_cfg = 4’d9) is driven high. 2'd3 = DSD 2'd2 = reserved 2'd1 = SPDIF 2'd0 = I2S (default) Selects the input to be used when the GPIO pin configured as input select (i.e. Register#8 gpio1_cfg = 4’d9 or Register#8 gpio2_cfg = 4’d9) is driven low. 2'd3 = DSD 2'd2 = reserved 2'd1 = SPDIF 2'd0 = I2S (default)

[3:0]

reserved

Register #64: Chip Status
8 bit, Read-Only Register Bits [7] [6] [5] Mnemonic Reserved Bit [7:5] [4:2] [1] [0] Mnemonic Reserved chip_id automute_status lock_status [4] [3] [2] chip_id [1] automute_status [0] lock_status

Description Chip ID 1'b1 => Automute condition is active. 1'b0 => Automute condition is inactive. 1'b1 => The Jitter Eliminator is locked to an incoming signal. 1'b0 => The Jitter Eliminator is not locked to an incoming signal.

Register #65: GPIO
8 bit, Read-Only Register Bits [7] [6] [5] [4] [3] Mnemonic reserved Bit [7:2] [1] [0] Mnemonic reserved gpio_I[1] gpio_I[0] Description Status of pin GPIO2 Status of pin GPIO1 [2] [1] [0] gpio_I

Register #69-66: DPLL Ratio
32 bit, Read-Only Register. Reg 69 are the MSB’s, Reg 66 are the LSB’s Bits [31:0] Mnemonic dpll_num This is a read-only 32bit value that can be used to calculate the sample rate. The sample rate (Fin) can be calculated using: 32 Fin = (DPLL_NUM * FMCLK) / 2 .
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Register #93-70: Channel Status
Reg 93 are the MSB’s, Reg 70 are the LSB’s Format is [191:0] These registers allow read back of the SPDIF channel status. The status definition is different for the consumer configuration and professional configuration. Please refer to the following two tables for details.

SPDIF CHANNEL STATUS - Consumer configuration
Address Offset 0 [7] Reserved [6] Reserved [5] 0:2Channel 1:4Channel [4] Reserved [3] 0:No-Preemph 1:Preemph [2] 0:CopyRight 1:Non-CopyRight [1] 0:Audio 1:Data [0] 0:Consumer 1:Professional

1

2

3

Category Code 0x00: General 0x01:Laser-Optical 0x02:D/D Converter 0x03:Magnetic 0x04:Digital Broadcast 0x05:Musical Instrument 0x06:Present A/D Converter 0x08:Solid State Memory 0x16:Future A/D Converter 0x19:DVD 0x40:Experimental Channel Number 0x0:Don't Care 0x1:A (Left) 0x2:B (Right) 0x3:C 0x4:D 0x5:E 0x6:F 0x7:G 0x8:H 0x9:I 0xA:J 0xB:K 0xC:L 0xD:M 0xE:N 0xF:O Reserved Reserved Clock Accuracy 0x0:Level 2 +-1000ppm 0x1:Level 1 +-50ppm 0x2:Level 3 variable pitch shifted

4

Reserved

Reserved

Reserved

Reserved

Source Number 0x0:Don't Care 0x1:1 0x2:2 0x3:3 0x4:4 0x5:5 0x6:6 0x7:G 0x8:8 0x9:9 0xA:10 0xB:11 0xC:12 0xD:13 0xE:14 0xF:15 Sample Frequency 0x0:44.1k 0x2:48k 0x3:32k 0x4:22.05k 0x6:24k 0x8:88.2k 0xA:96k 0xC:176.4k 0xE:192k Word Length: If Word Field Size=0 |If Word Field Size = 1 000=Not indicated |000=Not indicated 100 = 23bits |100 = 19bits 010 = 22bits |010 = 18bits 110 = 21bits |110 = 17bits 001 = 20bits |001 = 16bits 101 = 24bits |101 = 20bits

Word Field Size 0:Max 20bits 1:Max 24bits

5-23

Reserved

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SPDIF CHANNEL STATUS - Professional configuration
Address Offset 0 [7] [6] [5] lock: 0: locked 1: unlocked [4] [3] [2] [1] 0:Audio 1:Non-audio [0] 0:Consumer 1:Professional

sampling frequency: 00: not indicated (or see byte 4) 10: 48 kHz 01: 44.1 kHz 11: 32 kHz

emphasis: 000: Emphasis not indicated 001: No emphasis 011: CD-type emphasis 111: J-17 emphasis

1

User bit management: 0000: no indication 1000: 192-bit block as channel status 0100: As defined in AES18 1100: user-defined 0010: As in IEC60958-3 (consumer)

2

alignment level: 00: not indicated 10: –20 dB FS 01: –18.06 dB FS

Channel mode: 0000: not indicated (default to 2 ch) 1000: 2 channel 0100: 1 channel (monophonic) 1100: primary / secondary 0010: stereo 1010: reserved for user applications 0110: reserved for user applications 1110: SCDSR (see byte 3 for ID) 0001: SCDSR (stereo left) 1001: SCDSR (stereo right) 1111: Multichannel (see byte 3 for ID) Use of aux sample word: Source Word Length: 000: not defined, audio max 20 bits If max=20bits |If max=24bits 000=Not indicated |000=Not indicated 100: used for main audio, max 24 bits 010: used for coord, audio max 20 bits 100 = 23bits |100 = 19bits 110: reserved 010 = 22bits |010 = 18bits 110 = 21bits |110 = 17bits 001 = 20bits |001 = 16bits 101 = 24bits |101 = 20bits

3

4

5 6-9 10-13 14-17 18-21 22

Channel identification: if bit 7 = 0 then channel number is 1 plus the numeric value of bits 0-6 (bit reversed). if bit 7 = 1 then bits 4–6 define a multichannel mode and bits 0–3 (bit reversed) give the channel number within that mode. fs scaling: Sample frequency (fs): Reserved DARS (Digital audio reference signal): 0: no scaling 0000: not indicated 00: not a DARS 1: apply factor of 0001: 24 kHz 01: DARS grade 2 (+ / –10 ppm) 1 / 1.001 to value 0010: 96 kHz 10: DARS grade 1 (+ / –1 ppm) 1001: 22.05 kHz 11: Reserved 1010: 88.2 kHz 1011: 176.4 kHz 0011: 192 kHz 1111: User defined Reserved alphanumerical channel origin: four-character label using 7-bit ASCII with no parity. Bits 55, 63, 71, 79 = 0. alphanumerical channel destination: four-character label using 7-bit ASCII with no parity. Bits 87, 95, 103, 111 = 0. local sample address code: 32-bit binary number representing the sample count of the first sample of the channel status block. time of day code: 32-bit binary number representing time of source encoding in samples since midnight reliability flags 0: data in byte range is reliable 1: data in byte range is unreliable CRCC 00000000: not implemented X: error check code for bits 0–183

23

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APPLICATION DIAGRAM

(6.0 DACLB DACL

RECOMMENDED POWER-UP SEQUENCE

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~ ~ ~ ~ ~ ~

6DPHWLPHDV9&&$RUODWHU

6DPHWLPHDV'9&&RUODWHU

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$WSRZHUXSDVVHUW5(6(7%XQWLODWOHDVW PVDIWHUDOOH[WHUQDOSRZHUVXSSOLHV DQG ;,0&/.LIVXSSOLHGH[WHUQDOO\ DUHVWDELOL]HG

6XEVHTXHQWUHVHW VKRXOGEHDVVHUWHG IRUQVRUORQJHU

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ABSOLUTE MAXIMUM RATINGS
PAREMETER Storage temperature Voltage range for digital input pins ESD Protection Human Body Model (HBM) Machine Model (MM) RATING -65°C to 105°C -0.3V to DVCC+0.3V 2000V 200V

WARNING: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. WARNING: Electrostatic Discharge (ESD) can damage this device. Proper procedures must be followed to avoid ESD when handling this device.

RECOMMENDED OPERATING CONDITIONS
PAREMETER Operating temperature Power Supply (Internal DVDD) Digital power supply voltage Analog core supply voltage Analog power supply voltage Total Power Power Supply (External DVDD) Digital core supply voltage (*3) Digital power supply voltage Analog core supply voltage Analog power supply voltage Total Power Note
(*1) fs =44.1kHz, MCLK=22MHz, I2S input, output unloaded (*2) with RESETB held low

SYMBOL TA

CONDITIONS -20°C to 70°C Voltage 1.8V ± 5% or 3.3V ± 5% 3.3V ± 5% 3.3V ± 5%, Current nominal (*1) TBD mA TBD mA TBD mA TBD mW Current nominal (*1) TBD mA TBD mA TBD mA TBD mA TBD mW Current standby (*2) TBD mA TBD mA TBD mA TBD mW Current standby (*2) TBD mA TBD mA TBD mA TBD mA TBD mW

DVCC VCCA AVCC_L, AVCC_R

DVDD DVCC VCCA AVCC_L, AVCC_R

Voltage 1.3V ± 5% 1.8V ± 5% or 3.3V ± 5% 3.3V ± 5% 3.3V ± 5%,

DC ELECTRICAL CHARACTERISTICS
Symbol Parameter VIH VIL VOH VOL Minimum Maximum Unit Comments 0.4 0.2 V V V V High-level input voltage DVCC/2 + 0.4 Low-level input voltage High-level output voltage DVCC-0.2 Low-level output voltage

IOH = 100 uA IOL = 100 uA.

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XI / MCLK Timing
tMCH MCLK tMCL tMCY
Parameter MCLK pulse width high MCLK pulse width low MCLK cycle time MCLK duty cycle Symbol TMCH TMCL TMCY Min 4.5 4.5 10 45:55 Max Unit ns ns ns

55:45

Audio Interface Timing
tDCH DATA_CLK tDCL tDCY tDH DATA[2:1]
Valid
Don’t Care

tDS
Valid

Parameter DATA_CLK pulse width high DATA_CLK pulse width low DATA_CLK cycle time DATA_CLK duty cycle DATA set-up time to DATA_CLK rising edge DATA hold time to DATA_CLK rising edge

Symbol tDCH tDCL tDCY tDS tDH

Min 4.5 4.5 10 45:55 2 2

Max

Unit ns ns ns ns ns

55:45

Note: ? Audio data on DATA[2:1] are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time requirements relative to the rising edge of DATA_CLK ? For DSD Phase mode, the normal data (D0, D1, D2 .. on p.8) must satisfy the setup and hold time requirements relative to the rising edge of DATA_CLK. The complimentary data (D0, D1, etc.) will be ignored.

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ANALOG PERFORMANCE
Test Conditions (unless otherwise stated)
1. 2. 3. TA=25oC, AVCC=VCCA=DVCC=3.3V,, fs =44.1kHz, MCLK=27Mhz and 32-bit data SNR/DNR: A-weighted over 20-20kHz in averaging mode THD+N: un-weighted over 20-20kHz bandwidth

PARAMETER Resolution MCLK (PCM normal mode) MCLK (DSD mode) MCLK (SPDIF mode) DYNAMIC PERFORMANCE DNR (differential current mode) THD+N (differential current mode) ANALOG OUTPUT Differential (+ or -) voltage output range Differential (+ or -) voltage output offset Differential (+ or -) current output range (Note *1) Differential (+ or -) current output offset (Note *1) Digital Filter Performance De-emphasis error Mute Attenuation PCM Filter Characteristics (Sharp Roll Off) Pass band Stop band Group Delay PCM Filter Characteristics (Slow Roll Off) Pass band Stop band Group Delay

CONDITIONS

MIN

TYP 32 >192 >3 >386 127 -120 3.05 (0.924*AVCC) 1.65 (AVCC/2) 3.903 2.112 – 1000*Vg/781.25

MAX

UNIT Bits Fs Fs Fs dB-A dB V pp V mA pp mA

-60dBFS 0dBFS Full-scale out Bipolar zero out Full-scale out Bipolar zero out to virtual ground at voltage Vg (V)

±0.2 127 ±0.003dB -3dB < -115dB 0.454 0.49 0.546 35/fs ±0.05dB -3dB < -100dB 0.308 0.454 0.814 6.25/fs

dB dB fs fs fs s fs fs fs s

Note *1. Differential (+ or -) current output is equivalent to a differential (+ or -) voltage source in series with a 781.25Ω resistor. The differential (+ or -) voltage source has a peak-to-peak output range of 3.05V (0.924*AVCC) and an output offset of 1.65V (AVCC/2).

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PCM DE-EMPHASIS FILTER RESPONSE (32kHz)

PCM DE-EMPHASIS FILTER RESPONSE (44.1kHz)

PCM DE-EMPHASIS FILTER RESPONSE (48kHz)

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ES9018K2M Datasheet PCM SHARP ROLL-OFF FILTER RESPONSE

PCM SLOW ROLL-OFF FILTER RESPONSE

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DSD FILTER RESPONSE

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28 Pin QFN Mechanical Dimensions

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Reflow Process Considerations
For lead-free soldering, the characterization and optimization of the reflow process is the most important factor you need to consider. The lead-free alloy solder has a melting point of 217°C. This alloy requires a minimum reflow temperat ure of 235°C to ensure good wetting. The maximum reflow temperature is in the 245° C to 260° C range, depending on the package size (Table RPC2). This narrows the process window for lead-free soldering to 10° C to 20° C. The increase in peak reflow temperature in combination with the narrow process window makes the development of an optimal reflow profile a critical factor for ensuring a successful lead-free assembly process. The major factors contributing to the development of an optimal thermal profile are the size and weight of the assembly, the density of the components, the mix of large and small components, and the paste chemistry being used. Reflow profiling needs to be performed by attaching calibrated thermocouples well adhered to the device as well as other critical locations on the board to ensure that all components are heated to temperatures above the minimum reflow temperatures and that smaller components do not exceed the maximum temperature limits (Table RPC-2). To ensure that all packages can be successfully and reliably assembled, the reflow profiles studied and recommended by ESS are based on the JEDEC/IPC standard J-STD-020 revision D.1.
Figure RPC-1. IR/Convection Reflow Profile (IPC/JEDEC J-STD-020D.1)

Note: Reflow is allowed 3 times. Caution must be taken to ensure time between re-flow runs does not exceed the allowed time by the moisture sensitivity label. If the time elapsed between the re-flows exceeds the moisture sensitivity time bake the board according to the moisture sensitivity label instructions.

Manual Soldering: Allowed up to 2 times with maximum temperature of 350 degrees no longer than 3 seconds.

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Table RPC-1 Classification reflow profile Profile Feature Pb-Free Assembly Preheat/Soak Temperature Min (Tsmin) 150 ° C Temperature Max (Tsmax) 200 ° C Time (ts) from (Tsmin to Tsmax) 60-120 seconds Ramp-up rate (TL to Tp) 3° C/second max. Liquidous temperature (TL) 217 ° C Time (tL) maintained above TL 60-150 seconds Peak package body temperature For users Tp must not exceed the classification temp in (Tp) Table RPC-2. For suppliers Tp must equal or exceed the Classification temp in Table RPC-2. Time (tp)* within 5 ° C of the specified 30* seconds classification temperature (Tc), see Figure RPC-1 Ramp-down rate (Tp to TL) 6° C/second max. Time 25 ° C to peak temperature 8 minutes max. * Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
Note 1: All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug). If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e., dead-bug), Tp shall be within ± 2 ° C of the live-bug Tp and still meet the Tc requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body temperatures refer to JEP140 for recommended thermocouple use. Note 2: Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly profiles should be developed based on specific process needs and board designs and should not exceed the parameters in Table RPC-1. For example, if Tc is 260 ° C and time tp is 30 seco nds, this means the following for the supplier and the user. For a supplier: The peak temperature must be at least 260 ° C. The time above 255 ° C must be at least 3 0 seconds. For a user: The peak temperature must not exceed 260 ° C. The time above 255 ° C must not exceed 30 seco nds. Note 3: All components in the test load shall meet the classification profile requirements.

Table RPC-2 Pb-Free Process - Classification Temperatures (Tc)
Package Thickness <1.6 mm 1.6 mm - 2.5 mm >2.5 mm Volume mm3<350 260 ° C 260 ° C 250 ° C Volume mm3 350 2000 260 ° C 250 ° C 245 ° C Volume mm3 >2000 260 ° C 245 ° C 245 ° C

Note 1: At the discretion of the device manufacturer, but not the board assembler/user, the maximum peak package body temperature (Tp) can exceed the values specified in Table RPC-2. The use of a higher Tp does not change the classification temperature (Tc). Note 2: Package volume excludes external terminals (e.g., balls, bumps, lands, leads) and/or nonintegral heat sinks. Note 3: The maximum component temperature reached during reflow depends on package thickness and volume. The use of convection reflow processes reduces the thermal gradients between packages. However, thermal gradients due to differences in thermal mass of SMD packages may still exist.

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ORDERING INFORMATION
Part Number ES9018K2M Description Sabre
32

Package 28-pin QFN

Reference 32-bit Mobile Stereo Audio DAC

The letter K identifies the package type QFN.

Revision History
Revision 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.81 0.9 Date February 15, 2013 March 20, 2013 April 10, 2013 April 19, 2013 May 16, 2013 May 22, 2013 June 5, 2013 June 20, 2013 July 9, 2013 July 30, 2013 Notes Initial version Update pinout, package, features and register description Update audio interface diagram, I2C description Update pinout General update Update register default and operating temperature range Update pin description, recommended operation conditions and application diagram Update part number, DSD filter response, absolute maximum ratings, package drawing and ordering information. Add reflow profile. Update package drawing General update

No part of this publication may be reproduced, stored in a retrieval system, transmitted, or translated in any form or by any means, electronic, mechanical, manual, optical, or otherwise, without the prior written permission of ESS Technology, Inc. ESS Technology, Inc. makes no representations or warranties regarding the content of this document. All specifications are subject to change without prior notice. ESS Technology, Inc. assumes no responsibility for any errors contained herein. U.S. patents pending.

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